1. Field of the Invention
The present invention relates to the electronic design of integrated circuits, and more specifically to a method and apparatus for the functional verification of a target integrated circuit design.
2. Related Art
Functional verification is one of the steps in the design of many integrated circuits. Functional verification generally refers to determining whether a design (xe2x80x9ctarget designxe2x80x9d) representing an integrated circuit performs a function it is designed for. In a typical design process, a designer identifies the functions to be performed and designs a circuit using high-level languages (e.g., VHDL language well known in the relevant arts) to perform the identified functions. An example of a function may be to generate a predetermined output data corresponding to a given input data. Tools available in the industry are typically used to generate a lower-level design (e.g., at gate-level) from the design specified in a high-level language. The higher level languages are generally more understandable to a user (human-being) while the lower level languages are closer in representation to the physical implementation.
Usually, the lower level design is evaluated against input data to generate output data. A determination of the accuracy of a functional design may be made based on the output data. The manner in which input data is generated and output data is used for determination of accuracy may depend on the specific type of verification environment. For example, in an emulation environment, the target design receives input data in a xe2x80x9creal environmentxe2x80x9d usually having other components, whose operation can be relied on for accuracy. The target design is implemented to typically operate at least with these other components. By testing the target design in combination with these other components, functional verification of the target design can be performed. In general, a functional verification system operating in an emulation environment needs to generate output data values quickly such that the output data is available in a timely manner for the other components.
In contrast, in a simulation environment, a designer specifies pre-determined input data and evaluates the target design against the input data. The output data generated by the evaluation is examined to determine whether the design performs the desired functions. Once a designer is satisfied with a design, the data representing the design is sent for fabrication as an integrated circuit.
Accuracy in the functional verification is an important requirement in the design process for several reasons. For example, it is relatively less expensive to alter a circuit design prior to fabrication compared to redesigning and sending the design data for fabrication. In addition, it may require several weeks of time to redesign and complete fabrication again. Such levels of delays may be unacceptable, particularly in the high-technology markets where short design cycles are generally important.
In addition to accuracy, the verification step needs to scale well to the functional verification of integrated circuits of large sizes. That is, a verification systems needs to provide for verification of integrated circuit designs of large sizes. As is well known, an integrated circuit (semi-conductor chip) can include transistors of the order of a few millions, and the number has been increasing over time.
Furthermore, it is generally desirable that the verification step be completed quickly or with minimal internal computations. The speed of verification is particularly important in view of the increase in size and complexity of integrated circuits. To decrease the total design cycle time, it is desirable that the functional verification be completed quickly.
U.S. patent application entitled, xe2x80x9cFunctional Verification of Integrated Circuit Designsxe2x80x9d, Ser. No.: 09/097,874, Filed: Jun. 15, 1998, describes some functional verification systems in which a target design is partitioned into many combinatorial logic blocks connected by sequential elements (e.g., flip-flops) and with appropriate dependencies. The state tables corresponding to the logic blocks are evaluated and stored in multiple random access storage devices (RASDs).
The output corresponding to each input combination is stored such that the output is retrieved from the corresponding RASD when the input combination is provided as a memory address to the RASD. For example, assuming a four input combinatorial logic and a RASD having four bits address bus, if the output the combinatorial logic is to be a 1 corresponding to an input of 1011, a xe2x80x981xe2x80x99 is stored in the memory location corresponding to address 1011.
Cross-connects (XCONs) may interconnect the RASDs and enforce the dependencies which preserve the overall function of the target design. In general, the XCONs provide the outputs resulting from evaluation as memory addresses to RASDs. An XCON may be connected to multiple RASDs, and the XCON together with the connected RASDs may be referred to as a combinatorial logic output evaluator (CLOE).
In an approach described in the co-pending application noted above, each CLOE is connected to 16 other CLOEs (termed as neighbors). One of these CLOEs acts as a central CLOE to communicate with other groups of 16 CLOEs. In other words, if the output of a combinatorial logic evaluated in a first group and the output is to be provided as an input to a RASD in another group, the central CLOEs of the two groups may need to communicate to enable the necessary data transfer.
Such an approach may have several disadvantages. For example, the scheduling of evaluation of a combinatorial block may be undesirably complicated as the inputs may need to be communicated from several CLOEs and due to the xe2x80x98hierarchyxe2x80x99 in communication resulting from the central CLOE. Accordingly, the embodiments of the co-pending application may not be suitable in some environments.
Therefore, what is needed is a method and apparatus which enables the CLOE outputs to be communicated in an efficient manner such that the evaluations can be scheduled and performed quickly. In addition, the approach generally needs to allows for one or more of several related features such as tracing, verification of cycle based and non-cycle based designs, etc.
The present invention enables the state of many signals to be traced during functional verification of a target design. The signals represent outputs resulting from the evaluation of various combinatorial blocks and/or together forming the target design. Multiple signals are grouped into a cluster, with each cluster being identified by a cluster identifier. The evaluated outputs (present values) for each cluster are sent on a bus, with the present value of each signal being sent on a pre-specified bit position.
A previous state memory may be used to store the previous value for each of the signals. A mask memory is used to indicate the specific bit positions of the bus on which the outputs related to each cluster may be received. In other words, only some of the bit positions may be used for some of the clusters, and the mask indicates the valid positions having an evaluated output on the bus.
A trace controller receives a cluster identifier and the corresponding evaluated outputs on a bus. The trace controller compares the evaluated outputs with the previous values in the previous state memory at the mask positions indicated for the cluster (by the mask memory). If a change is detected, information as to the change in noted in a trace buffer.
According to an aspect of the present invention, each of the mask memory and the previous state memory may contain as many locations as the number of clusters, and each of the memories may contain locations having as many bits as the number of bits received on the bus. As a result, the cluster number can be used to access both the mask and the previous values for the cluster.
According to yet another aspect of the present invention, a push time signal may be asserted to cause trace controller to immediately generate an entry in the trace buffer indicating the reception of the push timer signal. The entry enables the present value of different signals to be ascertained at the time of assertion of the push timer signal.
Therefore, the present invention provides the ability to trace the state changes of various signals as any necessary information on the changes may be written into trace buffer.
The present invention allows tracing of signals to be performed without impeding the functional verification as the outputs of evaluations may be examined quickly due to the use of mask memory and previous state memory.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.